This invention relates to the field of digital logic circuits and in particular to flip-flop and latch circuits capable of operating at a wide range of speeds. For the purposes of this application, flip-flop circuits and latch circuits should be understood to be interchangeable. Flip-flops are digital logic circuits that are capable of storing one bit of memory. Flip-flops may be used to store data such as the value of a transient signal or the state of a state machine. Typically, flip-flops are synchronized with a clock signal. Flip-flops can be classified as static or dynamic. Static flip-flops often have a feedback loop of logic gates that can preserve its stored data value indefinitely while power is supplied, even if its clock signal is stopped.
Dynamic flip-flops are well-suited for high-speed operation. Dynamic flip-flops use the capacitive properties of portions of its circuit to store the data value. For example, a dynamic flip-flop can include a circuit node that is charged during a portion of a clock cycle with a voltage representing a data value. During the remaining portion of the clock cycle, this circuit node is disconnected from the input and allowed to float, thereby storing the voltage representing a data value. However, the voltage representing a data value will gradually decay, eventually resulting in loss of the data. To avoid this, dynamic flip-flops periodically recharge the voltage of data storage nodes. Typically, this recharging or refresh cycle is performed once per clock cycle and alleviates potential problems due to leakage.
Another leakage-related effect can cause a dynamic flip-flop to erroneously change its state in the middle of a clock cycle. These and other types of leakage effects typically become more pronounced as manufacturing processes are scaled down to smaller dimensions.
Some applications are designed to operate at a predetermined clock frequency or within a relatively narrow range of clock frequencies. Because of this, dynamic flip-flops can be designed so that the leakage effects do not have time between refresh operations to erroneously change their states or outputs. However, programmable devices such as field-programmable gate arrays often must support a wide range of clock frequencies, for example due to the constraints of different designs capable being implemented by programmable devices. For these applications, dynamic flip-flops that are designed to operate correctly at higher clock frequencies can malfunction at lower clock frequencies due to the increased time period between refresh operations, which allows leakage effects sufficient time to override the proper behavior of dynamic flip-flops.
It is therefore desirable for a dynamic flip-flop circuit to be able to operate over a wide range of clock frequencies without undesirable behavior arising from leakage effects.